Displaying tile data - half way there.

 A day off work today and I spent it loading the graphics ROM chip.

First task was in the simulator, where the mechanism is very similar to the real hardware but without SDRAM you need to instantiate some dual-port RAM in the simulator top-level Verilog module and code the logic to write the downloaded ROM data into RAM.

To test it I created the missing 'Pattern Plane Generator' sub-module from the YGV608 block diagram and then coded up some simple logic to display the first page of patterns (tiles) from the ROM with a fudged palette. After a few iterations of bug fixes I saw this...

The first page of tiles from the NCV1 graphics ROM

If you zoom in you can make out a shadowed character set, albeit upside-down due to the default orientation of the simulated video display. It does actually match the character set as displayed in MAME, so a good start!

Next step was to replicate this on MiSTer hardware. I borrowed (for now) the SDRAM controller from the Gauntlet project and studied how it multiplexed ROM download and video reads. It's fairly simple and again only a few iterations were required until I got video output again. Unfortunately the output is considerably less interesting than the output from the simulator...

Rather than showing tile data however, the active display area is a solid salmon pink (of all colours!) As a quick test I reflected the requested SDRAM address back as SDRAM data and got the expected cross-hatch pattern - so it's not a connectivity issue between the YGV608 core and the SDRAM. Furthermore (effectively) disabling download displays the same thing, suggesting it's the reads from SDRAM, not the writes to SDRAM that are failing (otherwise there'd be random data or data from the previously loaded Gauntlet core, for example).

So next session I'll continue to debug the SDRAM ROM issue.