I've finished the Quartus project pin assignments for both the CHA and PRG projects. I've also built the analyser configuration for each of those projects and they appear to build without issue. Nothing exciting here as each pin is configured as I/O and tri-stated so that the SignalTap analyser can be enabled. I've also confirmed there's enough memory on the device (EP3C16) for a decent trace.
The programmer function build for the CHA project includes a NIOS with sufficient PIO to drive the three (3) buses and - in theory - the FLASH control pins. I've hooked up the former, but not the latter. That's my next task on the list, before I attempt to write the programmer function software.
Once that's done I'll repeat the exercise for the PRG project, and we should be (almost) good to go for manufacture of the programmer/analyser PCB - it would be prudent to do further research on the known bank-switching and protection mechanisms in newer cartridges before committing the design to manufacture.
The programmer/analyser should (incidentally) also have the capability to operate as an MVS->AES converter board. No doubt there's some tweaking to be done in the sprite data serialisation, given the technical issues with most of the commercial converter boards. It's something I'll have to tackle on the flash cartridge eventually, as it will of course operate in both MVS & AES systems. I do not, however, have any intention of producing commercial converter boards; I'll leave that to those who have already done so. I have no desire to encroach on existing markets.
Realistically, I'm hoping to send out the PCB before the end of September.
Sunday 31 August 2014
Thursday 28 August 2014
Will it blend?
I'm thinking, in order to increase the desirability of a Neo Geo Motherboard replacement, of including a built-in esky with ice crusher, waterproof speakers, and USB charger.
Think it'll fly?
Think it'll fly?
Wednesday 20 August 2014
Analyse this!
Well, this is almost as much a shock to me as it will no doubt be to my thousands of two followers, but the analyser/programmer PCB is ready for manufacture! Yes, you read that right. From vague promises of a schematic in progress to a finished board in a single blog entry. Wow!
You see, my colleague has been toiling away on the design in between paid work which has been, unfortunately, quite sporadic for him lately. I knew he'd made some headway with the layout, but it came as a complete surprise when he presented me with the gerbers this afternoon!
Needless to say, I have a lot of catching up to do. I had started the HDL months ago, but that had languished on the back-burner whilst Lode Runner took all my spare time. Now I need to crank up Quartus again and finish it off, to ensure that the connectivity (eg. pin mapping) is correct and that the hardware design is adequate for the intended functionality.
And before I send out the board for manufacture, I also want to do a preliminary draft of the schematic for the flash cartridge, for the same reasons outlined above. And of course I need to do a thorough design review of the current PCB, so there's a fast growing pile of work on my plate.
Once manufactured, I'll be in a position to run the analyser functionality through its paces. The point was to obtain detailed bus timing diagrams for both CHA and PRG cartridge buses, via the Quartus SignalTap tool - information that will be invaluable for the FPGA implementation of the motherboard. The programmer functionality will only be useful when the next PCB - the flash cart - has been finished.
My final comment on the subject for this entry is that my dreams of hand-assembling the few (4?) boards that I will get loaded have been dashed by my colleague's rather... comprehensive... design practices. Suffice it to say, industrial strength power supplies and I/O protection are included as standard. I guess that means the production version won't require much in the way of a re-spin.
And a note on the possible Neo Geo port of Lode Runner I mentioned in the last entry; instead of producing a 68K translation I wrote a C version which should be (more) readily portable to any 16-bit or newer system. Progress here.
The next few updates on the analyser/programmer PCB should be a lot more frequent now!
You see, my colleague has been toiling away on the design in between paid work which has been, unfortunately, quite sporadic for him lately. I knew he'd made some headway with the layout, but it came as a complete surprise when he presented me with the gerbers this afternoon!
Needless to say, I have a lot of catching up to do. I had started the HDL months ago, but that had languished on the back-burner whilst Lode Runner took all my spare time. Now I need to crank up Quartus again and finish it off, to ensure that the connectivity (eg. pin mapping) is correct and that the hardware design is adequate for the intended functionality.
And before I send out the board for manufacture, I also want to do a preliminary draft of the schematic for the flash cartridge, for the same reasons outlined above. And of course I need to do a thorough design review of the current PCB, so there's a fast growing pile of work on my plate.
Once manufactured, I'll be in a position to run the analyser functionality through its paces. The point was to obtain detailed bus timing diagrams for both CHA and PRG cartridge buses, via the Quartus SignalTap tool - information that will be invaluable for the FPGA implementation of the motherboard. The programmer functionality will only be useful when the next PCB - the flash cart - has been finished.
My final comment on the subject for this entry is that my dreams of hand-assembling the few (4?) boards that I will get loaded have been dashed by my colleague's rather... comprehensive... design practices. Suffice it to say, industrial strength power supplies and I/O protection are included as standard. I guess that means the production version won't require much in the way of a re-spin.
And a note on the possible Neo Geo port of Lode Runner I mentioned in the last entry; instead of producing a 68K translation I wrote a C version which should be (more) readily portable to any 16-bit or newer system. Progress here.
The next few updates on the analyser/programmer PCB should be a lot more frequent now!
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