Adapters ready to go

Thanks mostly to my colleague who has been working hard on layout in his spare time, the adapter boards are ready to go out!

As promised, some eye candy, and I'll attempt to explain what they are and how they're going to be used for the project:

MVS Adapter Board (System Adapter configuration)

Both the AES and MVS adapter boards connect to the respective AES and MVS system boards and cartridges. Shown above is a 'system' adapter, with the card-edge connectors on the bottom side of the PCB. In this case a fingerboard (shown below) connects the adapter board to the system board. The adapter has been designed to (just) fit into a horizontal 1-slot MVS motherboard, although the size was ultimately constrained by routing requirements. We'll have to wait and see if it does actually fit when fully assembled.

MVS Fingerboard - system adapter to MVS board

At the cartridge end, the same adapter PCB is loaded with the card-edge and (opposite gender) EURO connectors mounted on opposite sides of the PCB. The AES/MVS cartridge plugs directly into the card-edge connector on this adapter.

Ultimately then, a pair (CHA & PRG) of analyser/programmer PCB's plug between the EURO connectors on the system and cartridge adapter boards. In the analyser configuration, the PCB snoops the cartridge bus accesses for display via the Altera Signal Tap analyser in the FPGA.

The analyser/programmer PCB also has a programmer configuration for the flash cartridge which I won't go into now.

The plan is to send the adapter and fingerboard PCB's out to be manufactured this week, and also order the rather expensive connectors from Digikey. When they're assembled they can be tested by plugging the cartridge and system adapters back-to-back via the EURO connectors, which should act as a completely passive pass-through on the MVS and AES systems.

AES Adapter Board (System Adapter configuration)

While we wait for the manufacture of the adapter boards, I'll press ahead with the design of the analyser/programmer board. I've chosen a candidate FPGA and have started on the HDL design of both analyser (trivial) and programmer functions. Once I've convinced myself that the FPGA is sufficient for the task, I'll start on schematic capture.