Thursday, 19 March 2015

Mid March Update

It's been a fortnight since the last update, and I'm pleased to say that there has been more progress again since then. I can't say how much longer it will take at this stage, but from appearances I'd estimate that approximately 70% of the layout is complete now. I'm secretly hoping that the closer it nears completion, the more David will be eager to complete it... and that this will be the last blog update before it is done.

Once layout is done I'll post a 3D rendering of the PCBA.

Thursday, 5 March 2015

Feb Update

I'm pleased to be able to say that my learned colleague is progressing well with layout of the flash cartridge prototype. Most of the component & connector placement has been finalised with routing for traces not connected to FPGA I/O pins nearing completion. Reportedly there's still a few weeks work remaining, based on his current time allocated to the project.

Aside from the above, there's not a lot else happening on the project. I've taken the FPGA HDL and software about as far as practical without actual hardware, so that's on hold, though it will probably be cracked open again when it's time to review the final flash cartridge schematic before production.

I've taken the opportunity to snap up a few cheap AES cartridges - for testing the main project of course. My latest acquisition was Art Of Fighting (1), which I was particularly interested in because the source code was found for it on a former developer's hard drive and is freely available for download on the net.

More when it happens...

Thursday, 15 January 2015

2015 and beyond

Part of my New Year resolutions is to be more productive with my time this year. I think 2015 is crunch time for this project, and if I don't get a move-on, someone is going to beat me to it. Whilst my spare time is going to be truly limited in the next 6-12 months, it's all about making the most of what little I do have, and not just whittling away the hours surfing the net.

Tune in here same time in 2016 to read me lamenting about this year and proclaiming the same resolutions next year.

Layout is continuing with my colleague in the process of morphing his analyzer PCB design (which was complete) into the flash cartridge. No ETA to report as he can only work on it in when his spare time and his motivation happen to coincide with one another. You get what you pay for! But I am happy to report at least that progress is being made, and the project isn't just languishing on the back-burner for months at a time as it has done so in the past.

I also managed to acquire Metal Slug 4 (MVS) - purely for this project of course. It had nothing to do with the fact that Metal Slug is my favourite franchise on the Neo Geo, if not any arcade platform. I should also resolve to actually play these games more and not just collect and emulate them!

Pretty much every reader of this blog has requested specifications of the flash cartridge, so at some point as layout nears completion I'll post those, along with a description of the 'bitmap mode' feature.

When layout is complete I should be able to post a 3D rendering of the PCB. There's simply nothing more exciting than being able to see vapourware in glorious full-colour 3D!

Friday, 19 December 2014

Xmas update

Work is continuing, albeit slowly, on the flash cartridge.

The schematics are all-but-complete, according to my colleague. The SRAM for a pseudo 'bitmap' mode has been included as well. I still need to discard a few debug pins on the design as the FPGA pin count has been exceeded on the CHR board, but otherwise it's all good.

I've created the FPGA design, the NIOS, and the software project for programming the flash. The FatFS module for reading from SD card has been compiled-in and it seems the EP3C16 will be adequate for the task (on-chip RAM being the critical resource). The prototypes will be loaded with the EP3C40 in any case.

Layout schedule will depend on the availability and the motivation of my colleague. Assuming he gets bored over the break, we might have something ready for review in January!

In the mean-time, I've acquired a 'sacrificial' (faulty palette but otherwise fully operational) AES console which turned out to be a bit of a Frankenstein. The case is for a 5V model but the motherboard is clearly a 10V design. But I have confirmed it powers up and runs a game.

I also acquired Metal Slug 3 for the MVS, which means I now have episodes 1-3, and I'm eyeing off 4 for a decent price on eBay right now. Of course this is for The Project, and not for playing (or for the sake of collecting). Right!

Thursday, 27 November 2014

Quick update

As mentioned, the re-think has reduced the PCB design count from 3 to 1.

This does make the cartridge configuration of the adapters obsolete, unfortunately. Whilst the PCB's themselves won't be wasted (same PCB for cartridge and system adapters) there's a few connectors that may be.

After taking a closer look at the protection and bank switching on the existing commercial cartridges, it soon became clear that an all-encompassing design would require an FPGA capable of snooping and/or routing almost every pin on the cartridge bus. So I've decided to scrap the analyzer/programmer PCB and have the flash cartridge capable of analyzing the bus and also programming itself.

The prototype design will be over-engineered somewhat; I want to address the Neo Geo technical issues without a half-baked design getting in the way. There may be scope for a limited run of this design, but it will be expensive. In any case I'd look at possibly two (2) products from this - a cheaper, cut-down Homebrew Edition that is suited to testing and playing homebrew titles only, and the full-blown Pro Gamer Edition that could, well, play any Neo Geo title.

I've also included some SRAM on the design, for the purpose of experimenting with dynamic sprite tile data. This would in effect allow for a bitmap display mode, opening up all sorts of possibilities for ports from other platforms (Defender, anyone?)

As for progress, all the devices have been specified and chosen, and schematic capture is under way. On the firmware side, the FPGA projects have been mapped out at the top level and a NIOS core has been added to the PRG project - mainly to gauge adequacy of the chosen FPGA.

I'm hoping things will progress quickly from here, as the design really is simple, and it's possible we could have the PCB's ready for manufacture this calendar year! It's not going to be a cheap process as they will need to be assembled externally, so timing may also depend on available funds.

Wednesday, 19 November 2014

Let there be only one

Major rethink of the project over the last few days. All good news though!

I won't go into too much detail as it's very late, but in a nutshell the programmer/analyzer board has been scrapped, and the 2-PCB flash cartridge (PRG & CHA) in the pipeline has been brought forward and replaced with a single PCB that is also a programmer/analyzer. IOW, a single PCB design will do everything that previously three (3) were intended to do!

This has all been prompted by more detailed analysis of the various cartridge protection (banking and encryption) schemes which, although not overly complex, require a lot of routing through an FPGA if it is to cater for every cartridge.

And adding to the mix is the possibility of adding a 'bitmap' mode to the Neo Geo via the cartridge!

More details in a subsequent post.

Thursday, 13 November 2014

Back in a flash!

Copping a lot of heat to get the Neo Geo flash cartridge finished off. To be honest, I'm feeling burnt out at work and the knock-on effect is that I don't feel motivated to do any computer-related activities in my own time either - even fun stuff like Neo Geo. So I find myself riding my bike and surfing the net...

However I'm making a concerted effort to get the grey matter ticking over and move things along now, particularly in light of the fact that come Jan 27th 2015 - or thereabouts - I'll have a lot less time for leisurely pursuits with the arrival of a little boy.

To this end, I decided to look at cartridge capacities and try to work out what size flash devices I'd need on a programmable flash cartridge. Keeping in mind that the prototype need only be large enough for a single game, I'd like the option for that to be ideally any game currently available for the Neo Geo! For the purposes of this exercise, I chose to use The King Of Fighters 2003 as a benchmark.

The numbers I ended up with (KOF2003 bracketed) are:
  • P-ROM (9MB) = 16MB/128Mb (x16)
  • C-ROM (64MB) = 64MB/512Mb (x32)
  • V-ROM (16MB) = 16MB/128Mb (TBA)
  • S-ROM (none) = 512KB/4Mb (x8)
  • M-ROM (512KB) = 512KB/4Mb (x8)
These are reasonable numbers for single/dual device solutions per bus, and flash is surprisingly cheap, so no big deal here. I could probably even double it if I felt the need. As it stands though, the proposed flash cartridge will therefore have a capacity of 776 MBits.

I want to get a preliminary design of the flash cartridge drafted before I commit the programmer/analyzer PCB to manufacture. However I need to do some more research on the bank switching and protection on the various carts before this task is complete. Either that or throw a large CPLD into the mix, and pass most of the address lines through it...