No putting it off any longer, I need the graphics ROM to be read from SDRAM.
Initial implementation today didn't go well. Getting the data into the SDRAM was trivial - the ROM LOADER module was already designed to do that after changing a single constant - but reading out has proven less successful.
The graphics ROM is accessed at 12MHz by the YGV608 - twice the dot-clock as it interleaves Planes A & B. That's just 83.3ns to get the data back from SDRAM given access latency, arbitration with the CPU ROM access, and refresh. The SDRAM itself is running 8x faster, so 8 clocks.
The bandwidth isn't really a problem, but the latency may well be. I need to sit down and actually calculate what I can theoretically expect from the SDRAM.
I can halve the number of accesses using a relatively simple read cache as every other - interleaved - read is from the same 16 bits, so that will help a little with bandwidth. But I'm thinking I might need to cache a whole line at the end of VBLANK (or better yet, during the BORDER) to avoid latency issues.
Either way, I've never implemented my own cache, so I need to do a little research first. It will probably end up as a 2-level cache; one for the 16-bit access and one for the whole line. Will be a fun learning exercise! Well, fun until I can't get it to work properly...
Happy New Year from 2024!
